39 search results - page 3 / 8 » Tolerating node failures in cache only memory architectures |
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Fault-tolerant distributed real-time systems are presently facing a lot of new challenges. Although many techniques provide effective masking of node failures on the architectural...
PRDC
2006
IEEE
14 years 1 months ago
2006
IEEE
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
ISPDC
2003
IEEE
14 years 21 days ago
2003
IEEE
As software Distributed Shared Memory(DSM) systems become attractive on larger clusters, the focus of attention moves toward improving the reliability of systems. In this paper, w...