We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...