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DATE
2005
IEEE
132views Hardware» more  DATE 2005»
14 years 3 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 3 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
DAC
2005
ACM
13 years 11 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
ICASSP
2011
IEEE
13 years 1 months ago
Weighted and structured sparse total least-squares for perturbed compressive sampling
Solving linear regression problems based on the total least-squares (TLS) criterion has well-documented merits in various applications, where perturbations appear both in the data...
Hao Zhu, Georgios B. Giannakis, Geert Leus
PPAM
2005
Springer
14 years 3 months ago
Total Exchange Performance Modelling Under Network Contention
Abstract. One of the most important collective communication patterns for scientific applications is the many to many, also called complete exchange. Although efficient All-to-All...
Luiz Angelo Steffenel, Grégory Mounié...