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» Toward Formalizing a Validation Methodology Using Simulation...
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ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 6 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
MSWIM
2006
ACM
14 years 2 months ago
Testing methodology for an ad hoc routing protocol
In this paper, we define a model of an ad hoc routing protocol, i.e. the OLSR (Optimized Link-State Routing) protocol. This model handles novel constraints related to such networ...
Stéphane Maag, Fatiha Zaïdi
TVLSI
2008
152views more  TVLSI 2008»
13 years 8 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 8 days ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
14 years 9 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...