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CGO
2004
IEEE
14 years 6 days ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
14 years 3 months ago
Increased accuracy through noise injection in abstract RTOS simulation
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
Henning Zabel, Wolfgang Mueller
IPPS
2003
IEEE
14 years 1 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
14 years 24 days ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
WADT
1999
Springer
14 years 22 days ago
From States to Histories
Based on the FOCUS theory of distributed systems (see [Broy, Stølen 01]) that are composed of interacting components we introduce a formal model of services and layered architectu...
Manfred Broy