145 search results - page 14 / 29 » Towards an efficient switch architecture for high-radix swit... |
ERSA
2010
13 years 5 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
EIT
2008
IEEE
13 years 9 months ago
2008
IEEE
Abstract--Real-time image and multimedia processing applications such as video surveillance and telemedicine can have dynamic requirements of system latency, throughput, and power ...
CDES
2008
13 years 9 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...