145 search results - page 4 / 29 » Towards an efficient switch architecture for high-radix swit... |
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
14 years 8 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
ICC
2000
IEEE
13 years 12 months ago
2000
IEEE
— We consider cell-based switch architectures in which the speedup of the internal switching fabric is not large enough to avoid input buffering. These architectures require a sc...
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
INFOCOM
1999
IEEE
13 years 11 months ago
1999
IEEE
With the proliferation of high-speed networks and networked services, provisioning differentiated services to a diverse user base with heterogeneous QoS requirements has become an ...