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ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
14 years 2 months ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
HPDC
2005
IEEE
14 years 2 months ago
A new metric for robustness with application to job scheduling
Scheduling strategies for parallel and distributed computing have mostly been oriented toward performance, while striving to achieve some notion of fairness. With the increase in ...
Darin England, Jon B. Weissman, Jayashree Sadagopa...
DAC
2009
ACM
14 years 9 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
DAC
2008
ACM
14 years 9 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
14 years 3 months ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang