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GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
CAISE
2006
Springer
14 years 2 months ago
Designing Security Requirements Models Through Planning
The quest for designing secure and trusted software has led to refined Software Engineering methodologies that rely on tools to support the design process. Automated reasoning mech...
Volha Bryl, Fabio Massacci, John Mylopoulos, Nicol...
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
14 years 2 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
ICSR
2000
Springer
14 years 2 months ago
Achieving Extensibility Through Product-Lines and Domain-Specific Languages: A Case Study
ions that are fundamental to simulators. We present preliminary results that show how our PLA and DSL synergistically produce a more flexible way of implementing state-machine-base...
Don S. Batory, Clay Johnson, Bob MacDonald, Dale v...
JAVACARD
2000
14 years 2 months ago
Automatic Test Generation for Java-Card Applets
: Open-cards have introduced a new life cycle for smart card embedded applications. In the case of Java Card, they have raised the problem of embedded object-oriented applet valida...
Hugues Martin, Lydie du Bousquet