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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
TIME
2006
IEEE
14 years 3 months ago
In time alone: on the computational power of querying the history
Querying its own history is an important mechanism in the computations, especially those interacting with people or other computations such as transaction processing, electronic d...
Alexei Lisitsa, Igor Potapov
HPDC
2005
IEEE
14 years 3 months ago
Increasing application performance in virtual environments through run-time inference and adaptation
Virtual machine distributed computing greatly simplifies the use of widespread computing resources by lowering the abstraction, benefiting both resource providers and users. Tow...
Ananth I. Sundararaj, Ashish Gupta, Peter A. Dinda
IEEEPACT
2005
IEEE
14 years 3 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
IEEEPACT
2005
IEEE
14 years 3 months ago
Store-Ordered Streaming of Shared Memory
Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming prov...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...