We compare the complexity of "internal" and "external" equivalence checking. The former is meant for proving the correctness of a synthesis transformation by w...
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gainbased Logic Blocks (GLBs). The GLB is a semi-univers...
Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek...
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...