Sciweavers

13 search results - page 3 / 3
» Transistor-Specific Delay Modeling for SSTA
Sort
View
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 4 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
14 years 4 months ago
A new statistical max operation for propagating skewness in statistical timing analysis
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylv...