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HPCA
2008
IEEE
14 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
SIGMOD
2009
ACM
137views Database» more  SIGMOD 2009»
14 years 10 months ago
Advances in flash memory SSD technology for enterprise database applications
The past few decades have witnessed a chronic and widening imbalance among processor bandwidth, disk capacity, and access speed of disk. According to Amdhal's law, the perfor...
Sang-Won Lee, Bongki Moon, Chanik Park
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 7 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
ICS
2009
Tsinghua U.
14 years 4 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
CLUSTER
2009
IEEE
14 years 4 months ago
Power-aware scheduling of virtual machines in DVFS-enabled clusters
—With the advent of Cloud computing, large-scale virtualized compute and data centers are becoming common in the computing industry. These distributed systems leverage commodity ...
Gregor von Laszewski, Lizhe Wang, Andrew J. Younge...