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IPPS
1999
IEEE
14 years 1 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
RAID
1999
Springer
14 years 1 months ago
Session State Transition Based Large Network IDS
In order to present large-scale malicious attacks on an ISP network to maintain network services, we have designed a method to record key packets classified by sessions. Session i...
Qianli Zhang, Xing Li
IPPS
1998
IEEE
14 years 1 months ago
Pin-Down Cache: A Virtual Memory Management Technique for Zero-Copy Communication
The overhead of copying data through the central processor by a message passing protocol limits data transfer bandwidth. If the network interface directly transfers the user'...
Hiroshi Tezuka, Francis O'Carroll, Atsushi Hori, Y...
ICS
1998
Tsinghua U.
14 years 29 days ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
DAC
1996
ACM
14 years 27 days ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman
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