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AOSD
2009
ACM
14 years 3 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
ENTCS
2010
111views more  ENTCS 2010»
13 years 6 months ago
Modular Verification of Interactive Systems with an Application to Biology
We propose an automata-based formalism for the description of biological systems that allows properties expressed in the universal fragment of CTL to be verified in a modular way....
Peter Drábik, Andrea Maggiolo-Schettini, Pa...
CAV
2007
Springer
111views Hardware» more  CAV 2007»
14 years 28 days ago
Verification Across Intellectual Property Boundaries
In many industries, the share of software components provided by third-party suppliers is steadily increasing. As the suppliers seek to secure their intellectual property (IP) righ...
Sagar Chaki, Christian Schallhart, Helmut Veith
IEICET
2006
114views more  IEICET 2006»
13 years 9 months ago
Synchronization Verification in System-Level Design with ILP Solvers
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro ...
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 6 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...