32 search results - page 4 / 7 » Trident: From High-Level Language to Hardware Circuitry |
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
ERSA
2008
13 years 10 months ago
2008
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
DAC
2006
ACM
14 years 2 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
VSTTE
2005
Springer
14 years 2 months ago
2005
Springer
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...