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FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 2 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
CGO
2004
IEEE
14 years 8 days ago
Using Dynamic Binary Translation to Fuse Dependent Instructions
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
Shiliang Hu, James E. Smith
ICSE
2008
IEEE-ACM
14 years 8 months ago
Continuous software quality supervision using SourceInventory and Columbus
Several tools and methods for source code quality assurance based on static analysis finally reached a state when they are applicable in practice and recognized by the industry. H...
Árpád Beszédes, Rudolf Ferenc...
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
14 years 3 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...