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» Two efficient methods to reduce power and testing time
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CORR
2010
Springer
91views Education» more  CORR 2010»
13 years 5 months ago
Joint space and workspace analysis of a two-DOF closed-chain manipulator
: The aim of this paper is to compute of the generalized aspects, i.e. the maximal singularity-free domains in the Cartesian product of the joint space and workspace, for a planar ...
Damien Chablat
DAC
2001
ACM
14 years 9 months ago
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
This paper addresses battery-aware static scheduling in batterypowered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level ...
Jiong Luo, Niraj K. Jha
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 2 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
DAC
1995
ACM
13 years 12 months ago
Efficient Power Estimation for Highly Correlated Input Streams
- Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the ...
Radu Marculescu, Diana Marculescu, Massoud Pedram
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 1 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...