524 search results - page 9 / 105 » Two efficient methods to reduce power and testing time |
BMCBI
2010
13 years 7 months ago
2010
Background: Computational comparison of two protein structures is the starting point of many methods that build on existing knowledge, such as structure modeling (including modeli...
ICRA
2002
IEEE
14 years 9 days ago
2002
IEEE
In this paper we present an approach to obstacle avoidance and local path planning for polygonal robots. It decomposes the task into a model stage and a planning stage. The model ...
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....