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VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 9 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
TCBB
2010
96views more  TCBB 2010»
13 years 3 months ago
A Survey of Spatial Defects in Homo Sapiens Affymetrix GeneChips
Modern biology has moved from a science of individual measurements to a science where data are collected on an industrial scale. Foremost, among the new tools for biochemistry are ...
William B. Langdon, Graham J. G. Upton, Renata da ...
IEEEPACT
2009
IEEE
14 years 3 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
IISWC
2008
IEEE
14 years 3 months ago
PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors
The PARSEC benchmark suite was recently released and has been adopted by a significant number of users within a short amount of time. This new collection of workloads is not yet ...
Christian Bienia, Sanjeev Kumar, Kai Li
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 3 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...