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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 7 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
CIDR
2011
401views Algorithms» more  CIDR 2011»
14 years 7 months ago
DBease: Making Databases User-Friendly and Easily Accessible
Structured query language (SQL) is a classical way to access relational databases. Although SQL is powerful to query relational databases, it is rather hard for inexperienced user...
Guoliang Li, Ju Fan, Hao Wu, Jiannan Wang, Jianhua...
ASPLOS
2009
ACM
16 years 4 months ago
CTrigger: exposing atomicity violation bugs from their hiding places
Multicore hardware is making concurrent programs pervasive. Unfortunately, concurrent programs are prone to bugs. Among different types of concurrency bugs, atomicity violation bu...
Soyeon Park, Shan Lu, Yuanyuan Zhou
ATAL
2007
Springer
15 years 10 months ago
Goals in the context of BDI plan failure and planning
We develop a Belief-Desire-Intention (BDI) style agent-oriented programming language with special emphasis on the semantics of goals in the presence of the typical BDI failure han...
Sebastian Sardiña, Lin Padgham
RTCSA
2006
IEEE
15 years 10 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue