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DAC
2007
ACM
14 years 8 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 2 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
RTAS
2011
IEEE
12 years 11 months ago
End-to-End Delay Analysis for Fixed Priority Scheduling in WirelessHART Networks
—The WirelessHART standard has been specifically designed for real-time communication between sensor and actuator devices for industrial process monitoring and control. End-toen...
Abusayeed Saifullah, You Xu, Chenyang Lu, Yixin Ch...
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
CDC
2008
IEEE
125views Control Systems» more  CDC 2008»
13 years 7 months ago
Efficient waypoint tracking hybrid controllers for double integrators using classical time optimal control
This paper is a response to requests from several respected colleagues in academia for a careful writeup of the classical time-optimal control based hybrid controllers that we have...
Haitham A. Hindi, Lara S. Crawford, Rong Zhou, Cra...