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131
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PTS
1998
81views Hardware» more  PTS 1998»
15 years 5 months ago
Testing Temporal Logic Properties in Distributed Systems
Based on the notion of event-based behavioral abstraction EBBA we specify properties of object-oriented distributed systems in linear time temporal logic. These properties are the...
Falk Dietrich, Xavier Logean, Shawn Koppenhoefer, ...
INTEGRATION
2006
102views more  INTEGRATION 2006»
15 years 4 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
ASWEC
2004
IEEE
15 years 8 months ago
An Environment for Automated Performance Evaluation of J2EE and ASP.NET Thin-client Architectures
Assessing the likely run-time performance of applications using thin-client architectures during their design is very difficult. We describe SoftArch/Thin, a thin-client test-bed ...
John C. Grundy, Zhong Wei, Radu Nicolescu, Yuhong ...
153
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ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
15 years 9 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
FPGA
2008
ACM
146views FPGA» more  FPGA 2008»
15 years 5 months ago
FPGA-optimised high-quality uniform random number generators
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
David B. Thomas, Wayne Luk