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» Ultra low power digital signal processing
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ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 3 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
ICASSP
2011
IEEE
13 years 23 days ago
Convex approximation algorithms for back-pressure power control of wireless multi-hop networks
Cross-layer design and operation of wireless networks has attracted significant interest in the last decade, yet some basic problems in the area remain unsolved. In this paper, w...
Evaggelia Matskani, Nikos D. Sidiropoulos, Leandro...
ISCAS
2005
IEEE
185views Hardware» more  ISCAS 2005»
14 years 2 months ago
2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu
ISCAS
2007
IEEE
124views Hardware» more  ISCAS 2007»
14 years 3 months ago
CMOS Current-controlled Oscillators
— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit curren...
Junhong Zhao, Chunyan Wang
ICASSP
2011
IEEE
13 years 23 days ago
Fast estimation of the state of the power grid using synchronized phasor measurements
—Both the communication limitation and the measurement properties based algorithm become the bottleneck of enhancing the traditional power system state estimation speed. The avai...
Tao Yang, Anjan Bose