76 search results - page 4 / 16 » Ultra-low power digital subthreshold logic circuits |
DSD
2008
IEEE
14 years 3 months ago
2008
IEEE
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using Low Temperature Polycrystalline Silicon ...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...