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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
ATVA
2006
Springer
191views Hardware» more  ATVA 2006»
14 years 1 months ago
Automatic Verification of Hybrid Systems with Large Discrete State Space
We address the problem of model checking hybrid systems which exhibit nontrivial discrete behavior and thus cannot be treated by considering the discrete states one by one, as most...
Werner Damm, Stefan Disch, Hardi Hungar, Jun Pang,...
SPIN
2000
Springer
14 years 1 months ago
The Temporal Rover and the ATG Rover
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
Doron Drusinsky
DLOG
2007
14 years 16 days ago
Optimizing Tableau Reasoning in ALC Extended with Uncertainty
Abstract. There has been an increased interest in recent years to incorporate uncertainty in Description Logics (DLs), and a number of proposals have been put forward for modeling ...
Volker Haarslev, Hsueh-Ieng Pai, Nematollaah Shiri
CODES
2006
IEEE
14 years 5 days ago
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buff...
Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, ...