In this work we reduce interconnect power dissipation in Symmetric Multiprocessors or SMPs. We revisit snoopy cache coherence protocols and reduce unnecessary interconnect activit...
Abstract. We consider systems of finite automata performing together computation on an input string. Each automaton has its own read head that moves independently of the other head...
Pavol Duris, Tomasz Jurdzinski, Miroslaw Kutylowsk...
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...