1052 search results - page 73 / 211 » Understanding POWER multiprocessors |
NOCS
2009
IEEE
14 years 4 months ago
2009
IEEE
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
ISCA
2007
IEEE
14 years 4 months ago
2007
IEEE
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
NOCS
2007
IEEE
14 years 4 months ago
2007
IEEE
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...