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» Understanding POWER multiprocessors
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ISPASS
2009
IEEE
14 years 4 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ISPASS
2005
IEEE
14 years 3 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...
DATE
2010
IEEE
153views Hardware» more  DATE 2010»
13 years 8 months ago
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem
— Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing pe...
Camille Jalier, Didier Lattard, Ahmed Amine Jerray...
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 3 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
EUMAS
2006
13 years 11 months ago
Coordinating Tasks in Agent Organizations
Abstract. Support for new forms of organization and social interaction requires understanding the influence of structure on behavior. Goal dependencies indicate some relationship b...
Virginia Dignum, Frank Dignum