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ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 5 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 5 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
TCAD
2010
116views more  TCAD 2010»
13 years 2 months ago
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
Anand Rajaram, David Z. Pan
ICASSP
2011
IEEE
12 years 11 months ago
Further analysis of latent affective mapping for naturally expressive speech synthesis
An essential step in the generation of expressive speech synthesis is the automatic detection and classification of emotions most likely to be present in textual input. At last I...
Jerome R. Bellegarda
UAI
2003
13 years 9 months ago
Practically Perfect
We prove that perfect distributions exist when using a finite number of bits to represent the parameters of a Bayesian network. In addition, we provide an upper bound on the prob...
Christopher Meek, David Maxwell Chickering