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ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
13 years 10 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
CGO
2003
IEEE
14 years 2 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 2 months ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
CORR
2004
Springer
121views Education» more  CORR 2004»
13 years 10 months ago
Worst-Case Optimal Tree Layout in a Memory Hierarchy
Consider laying out a fixed-topology tree of N nodes into external memory with block size B so as to minimize the worst-case number of block memory transfers required to traverse ...
Erik D. Demaine, John Iacono, Stefan Langerman
ISPASS
2005
IEEE
14 years 4 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...