720 search results - page 43 / 144 » Uniform Memory Hierarchies |
149
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QEST
2007
IEEE
15 years 10 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
126
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ASPLOS
2008
ACM
15 years 6 months ago
2008
ACM
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these opti...
121
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GLVLSI
1999
IEEE
15 years 8 months ago
1999
IEEE
We present a formalism for implementing circuits with Quantum-dot Cellular Automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism s...
106
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FOCS
2009
IEEE
15 years 11 months ago
2009
IEEE
In the classical balls-and-bins paradigm, where n balls are placed independently and uniformly in n bins, typically the number of bins with at least two balls in them is Θ(n) and ...
125
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MICRO
2009
IEEE
15 years 11 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...