720 search results - page 50 / 144 » Uniform Memory Hierarchies |
126
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SCI
1999
Springer
15 years 8 months ago
1999
Springer
This paper describes the parallelization of a commercial molecular dynamics simulation code, GROMOS96, on a SCI (Scalable Coherent Interface) interconnected PC cluster. The underly...
119
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ISCA
2009
IEEE
15 years 11 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
138
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ISCA
2009
IEEE
15 years 11 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
141
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SC
1992
ACM
15 years 8 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
176
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IEEEPACT
2009
IEEE
15 years 2 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...