33 search results - page 5 / 7 » Unifying behavioral synthesis and physical design |
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
GRAPHICSINTERFACE
2001
13 years 8 months ago
2001
Physics-based modeling integrates dynamics and geometry. The standard methods to solve the Lagrangian equations use a direct approach in the spatial domain. Though extremely power...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
NEUROSCIENCE
2001
Springer
13 years 12 months ago
2001
Springer
We propose a theoretical framework for specification and analysis of a class of learning problems that arise in open-ended environments that contain multiple, distributed, dynamic...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...