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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
13 years 12 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
ASPDAC
2007
ACM
124views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
Ajay K. Verma, Paolo Ienne
ASPDAC
2007
ACM
139views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Deeper Bound in BMC by Combining Constant Propagation and Abstraction
ound in BMC by Combining Constant Propagation and Abstraction Roy Armoni, Limor Fix1 , Ranan Fraer1 , Tamir Heyman1,3 , Moshe Vardi2 , Yakir Vizel1 , Yael Zbar1 1 Logic and Validat...
Roy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, ...
SAMOS
2004
Springer
14 years 27 days ago
A Novel Data-Path for Accelerating DSP Kernels
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty