Sciweavers

94 search results - page 16 / 19
» Unsynchronized Parallel Discrete Event Simulation
Sort
View
DAC
2010
ACM
13 years 7 months ago
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yun...
WSC
2007
13 years 9 months ago
Modeling and simulation for customer driven manufacturing system design and operations planning
Agility, speed and flexibility in production networks are required in today's global competition in the flat world. The accuracy of order date delivery promises is a key elem...
Juhani Heilala, Jari Montonen, Arttu Salmela, Pasi...
EUROPAR
2008
Springer
13 years 9 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
WSC
2000
13 years 8 months ago
Optimizing production work flow using OpEMCSS
A graphical discrete event simulation library is proposed for system simulation that is based on interacting concurrent processes. This library works with EXTEND (Imagine That Inc...
John R. Clymer
ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
11 years 9 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...