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CODES
2005
IEEE
15 years 9 months ago
FlexPath NP: a network processor concept with application-driven flexible processing paths
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild
CIKM
2010
Springer
15 years 2 months ago
Rank learning for factoid question answering with linguistic and semantic constraints
This work presents a general rank-learning framework for passage ranking within Question Answering (QA) systems using linguistic and semantic features. The framework enables query...
Matthew W. Bilotti, Jonathan L. Elsas, Jaime G. Ca...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 10 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
15 years 11 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
16 years 4 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...