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148
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 10 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 10 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
EAGC
2004
Springer
15 years 10 months ago
Overview of an Architecture Enabling Grid Based Application Service Provision
In this short paper we examine the integration of three emerging trends in Information Technology (Utility Computing, Grid Computing, and Web Services) into a new Computing paradig...
Stefan Wesner, Bassem Serhan, Theodosis Dimitrakos...
147
Voted
WECWIS
2007
IEEE
131views ECommerce» more  WECWIS 2007»
15 years 11 months ago
Event Cloud - Searching for Correlated Business Events
Market players that can respond to critical business events faster than their competitors will end up as winners in the fast moving economy. Event-based systems have been develope...
Szabolcs Rozsnyai, Roland Vecera, Josef Schiefer, ...
141
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ICSE
1999
IEEE-ACM
15 years 9 months ago
Information Survivability Control Systems
We address the dependence of critical infrastructures— including electric power, telecommunications, finance and transportation—on vulnerable information systems. Our approach...
Kevin J. Sullivan, John C. Knight, Xing Du, Steve ...