Given an image, we propose a hierarchical generative
model that classifies the overall scene, recognizes and segments
each object component, as well as annotates the image
with ...
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
We present an interactive and multi-level abstraction framework for user-generated video (UGV) summarisation, allowing a user the flexibility to select a summarisation criterion ...