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» Using Decision Diagrams to Design ULMs for FPGAs
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SIGADA
2001
Springer
13 years 12 months ago
Electronic maneuvering board and dead reckoning tracer decision aid for the officer of the deck
Statement and AbstractProblem Statement and AbstractProblem Statement and AbstractProblem Statement and Abstract The U.S. Navy currently bases the majority of our contact managemen...
Kenneth L. Ehresman, Joey L. Frantzen
DAC
2003
ACM
14 years 8 months ago
Symbolic representation with ordered function templates
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
Amit Goel, Gagan Hasteer, Randal E. Bryant
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 1 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
14 years 25 days ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
DAC
2009
ACM
14 years 8 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler