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GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
14 years 1 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
CCGRID
2011
IEEE
12 years 11 months ago
A Segment-Level Adaptive Data Layout Scheme for Improved Load Balance in Parallel File Systems
Abstract—Parallel file systems are designed to mask the everincreasing gap between CPU and disk speeds via parallel I/O processing. While they have become an indispensable compo...
Huaiming Song, Yanlong Yin, Xian-He Sun, Rajeev Th...
SIGMOD
2010
ACM
362views Database» more  SIGMOD 2010»
13 years 2 months ago
Data warehousing and analytics infrastructure at facebook
Scalable analysis on large data sets has been core to the functions of a number of teams at Facebook - both engineering and nonengineering. Apart from ad hoc analysis of data and ...
Ashish Thusoo, Zheng Shao, Suresh Anthony, Dhruba ...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 1 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
DATE
2006
IEEE
126views Hardware» more  DATE 2006»
14 years 1 months ago
Analysis and modeling of power grid transmission lines
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
J. Balachandran, Steven Brebels, G. Carchon, T. We...