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CODES
2006
IEEE
13 years 9 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
HPDC
2012
IEEE
11 years 10 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
CANPC
1999
Springer
14 years 1 days ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
AOSD
2008
ACM
13 years 9 months ago
Edicts: implementing features with flexible binding times
In a software product line, the binding time of a feature is the time at which one decides to include or exclude a feature from a product. Typical binding site implementations are...
Venkat Chakravarthy, John Regehr, Eric Eide