643 search results - page 26 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
ICCS
2004
Springer
14 years 2 months ago
2004
Springer
On cc-NUMA multi-processors, the non-uniformity of main memory latencies motivates the need for co-location of threads and data. We call this special form of data locality, geogra...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
TCAD
2008
13 years 8 months ago
2008
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...