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IISWC
2009
IEEE
14 years 2 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
13 years 11 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
ISPASS
2010
IEEE
14 years 2 months ago
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
—Until recently, most high-end scientific applications have been immune to performance problems caused by NonUniform Memory Access (NUMA). However, current trends in micro-proces...
Collin McCurdy, Jeffrey S. Vetter
PLDI
2009
ACM
14 years 2 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
CAL
2006
13 years 7 months ago
A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator
Modern programming languages often include complex mechanisms for dynamic memory allocation and garbage collection. These features drive the need for more efficient implementation ...
Wentong Li, Saraju P. Mohanty, Krishna M. Kavi