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DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 9 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
ISPASS
2009
IEEE
14 years 3 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
SIGMETRICS
2010
ACM
160views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
RSIO: automatic user interaction detection and scheduling
We present RSIO, a processor scheduling framework for improving the response time of latency-sensitive applications by monitoring accesses to I/O channels and inferring when user ...
Haoqiang Zheng, Jason Nieh
HOTI
2008
IEEE
14 years 3 months ago
Constraint Repetition Inspection for Regular Expression on FPGA
— Recent network intrusion detection systems (NIDS) use regular expressions to represent suspicious or malicious character sequences in packet payloads in a more efficient way. ...
Miad Faezipour, Mehrdad Nourani
HPCA
2001
IEEE
14 years 9 months ago
Dynamic Branch Prediction with Perceptrons
This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron as an alternative to the commonly used ...
Daniel A. Jiménez, Calvin Lin