Sciweavers

643 search results - page 62 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
ASPLOS
2000
ACM
14 years 1 months ago
Power Aware Page Allocation
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory ...
Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schl...
ISQED
2005
IEEE
140views Hardware» more  ISQED 2005»
14 years 2 months ago
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...
Aaron N. Ng, Igor L. Markov
ACMMSP
2005
ACM
106views Hardware» more  ACMMSP 2005»
14 years 2 months ago
Impact of modern memory subsystems on cache optimizations for stencil computations
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
Shoaib Kamil, Parry Husbands, Leonid Oliker, John ...
ASPLOS
2009
ACM
14 years 9 months ago
Dynamic prediction of collection yield for managed runtimes
The growth in complexity of modern systems makes it increasingly difficult to extract high-performance. The software stacks for such systems typically consist of multiple layers a...
Michal Wegiel, Chandra Krintz
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 1 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean