643 search results - page 66 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
HPCA
2002
IEEE
14 years 9 months ago
2002
IEEE
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
SPAA
1996
ACM
14 years 26 days ago
1996
ACM
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
IEEEPACT
2007
IEEE
14 years 3 months ago
2007
IEEE
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
PDPTA
2007
13 years 10 months ago
2007
We have developed a mobile thin-client server named ”HTTP-FUSE-KNOPPIX-BOX” that incorporates mechanisms for increasing performance, distributing load, and providing fault tole...