Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logicmemory architectures in addressing many of these issues has been recognized in general-purpose computing, and more recently in ASIC design. However, such architectures will be adopted widely by designers only when general techniques and tools for efficient high-level synthesis (HLS) of multi-partitioned ASICs become available. The techniques presented in this paper are motivated by the fact that many memoryintensive applications exhibit irregular array data access patterns (due to conditionals in loop nests, etc.). Synthesis should, therefore, be capable of determining a partitioned architecture, wherein array data and computations may have to be heterogeneously distributed for achieving the best performance speedup. Furthermore, the synthesis meth...

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
• Keywords: Array Data Access, Array Data References, Array Index Functions, Hardware, ICCAD 2003