Sciweavers

643 search results - page 72 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 1 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 3 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
ASPLOS
2008
ACM
13 years 10 months ago
Hardbound: architectural support for spatial safety of the C programming language
The C programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. C'...
Joe Devietti, Colin Blundell, Milo M. K. Martin, S...
SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
13 years 10 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
SIGMETRICS
1999
ACM
14 years 1 months ago
Availability and Utility of Idle Memory in Workstation Clusters
In this paper, we examine the availability and utility of idle memory in workstation clusters. We attempt to answer the following questions. First, how much of the total memory in...
Anurag Acharya, Sanjeev Setia