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ICPR
2000
IEEE
14 years 1 months ago
Transparent Parallel Image Processing by way of a Familiar Sequential API
This paper describes an infrastructure that enables transparent development of image processing software for parallel computers. The infrastructure’s main component is an image ...
Frank J. Seinstra, Dennis Koelma
JUCS
2007
122views more  JUCS 2007»
13 years 8 months ago
A New Architecture for Concurrent Lazy Cyclic Reference Counting on Multi-Processor Systems
: Multi-processor systems have become the standard in current computer architectures. Software developers have the possibility to take advantage of the additional computing power a...
Andrei de Araújo Formiga, Rafael Dueire Lin...
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
14 years 1 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
HPCA
2008
IEEE
14 years 9 months ago
Performance-aware speculation control using wrong path usefulness prediction
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Pa...
SIGMETRICS
2009
ACM
151views Hardware» more  SIGMETRICS 2009»
14 years 3 months ago
MapReduce optimization using regulated dynamic prioritization
We present a system for allocating resources in shared data and compute clusters that improves MapReduce job scheduling in three ways. First, the system uses regulated and user-as...
Thomas Sandholm, Kevin Lai